
28
4109LS–8051–02/08
AT8xC51SND1C
7.3.3.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 30. External IDE 16-bit Bus Cycle - Data Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Table 31. External IDE 16-bit Bus Cycle - Data Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Unit
Min
Max
Min
Max
TCLCL
Clock Period
50
ns
TLHLL
ALE Pulse Width
2TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
TCLCL-20
0.5TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5TCLCL-20
ns
TLLRL
ALE Low to RD Low
3TCLCL-30
1.5TCLCL-30
ns
TRLRH
RD Pulse Width
6TCLCL-25
3TCLCL-25
ns
TRHLH
RD high to ALE High
TCLCL-20
TCLCL+20
0.5TCLCL-20 0.5TCLCL+20
ns
TAVDV
Address Valid to Valid Data In
9TCLCL-65
4.5TCLCL-65
ns
TAVRL
Address Valid to RD Low
4TCLCL-30
2TCLCL-30
ns
TRLDV
RD Low to Valid Data
5TCLCL-30
2.5TCLCL-30
ns
TRLAZ
RD Low to Address Float
0
ns
TRHDX
Data Hold After RD High
0
ns
TRHDZ
Data Float After RD High
2TCLCL-25
TCLCL-25
ns
Symbol
Parameter
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Unit
Min
Max
Min
Max
TCLCL
Clock Period
50
ns
TLHLL
ALE Pulse Width
2TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
TCLCL-20
0.5TCLCL-20
ns
TLLAX
Address hold after ALE Low
TCLCL-20
0.5TCLCL-20
ns
T
LLWL
ALE Low to WR Low
3T
CLCL-30
1.5T
CLCL-30
ns
T
WLWH
WR Pulse Width
6T
CLCL-25
3T
CLCL-25
ns
T
WHLH
WR High to ALE High
T
CLCL-20
T
CLCL+20
0.5T
CLCL-20
0.5T
CLCL+20
ns
T
AVWL
Address Valid to WR Low
4T
CLCL-30
2T
CLCL-30
ns
T
QVWH
Data Valid to WR High
7T
CLCL-20
3.5T
CLCL-20
ns
T
WHQX
Data Hold after WR High
T
CLCL-15
0.5T
CLCL-15
ns